The present invention relates to a bus architecture for a packet-switched computer system which accommodates master, slave and memory devices having buses of various sizes, different from one another and different from the size of the system bus.
Computers are being designed today and for the foreseeable future with ever greater bus sizes, to handle the increasing throughput possible with very fast microprocessors. Typically, the bus architecture in a computer system is sized to accommodate the CPU, to allow for very fast transfers. For example, in today""s workstations a databus width of 144 bits is common in highend machines, while in the next generation of systems, databus widths of 288 bits will be used.
In today""s systems, a bus having a width of a given number of bits requires that all functional units connected to the bus interface to that entire bus width. However, many devices are not designed to use the entire bus width, and hence there is waste of unused bandwidth. It is wasteful and expensive to design the functional units to accommodate the entire bus width when they cannot take advantage of it. (A reverse situation can also occur: functional devices such as memory may have bus widths larger than the databus width.)
A new type of system is needed wherein a large bus width does not require that functional units coupled to it be of the same bus size, and in particular that allows devices of smaller bus size to be coupled to a large-databus architecture without loss of data or inefficiencies through the loss of clock cycles or transmission of data that go unused because of bus size incompatibility.
Such a system must also accommodate devices coupled to the system bus that have bus sizes that are larger than that of the system bus.
A system controller for a packet-switched computer system is provided with subsystems for adapting the transference of data words from a large system bus to a smaller device bus, and additionally to a larger device bus. A bus device table is provided, which includes information about the data bus width for each connected device. The system controller receives a request to transfer data from a master device such as the processor to a slave device, which may be any device that can receive data.
The system controller determines the size of the slave""s bus, and if the slave bus is smaller than the master""s bus then the system controller adapts the transfer rate accordingly by sending data to the slave device at a rate which is suitable for its bus size. Alternatively, a data buffer is provided and the system controller sends the data at substantially the full rate for its bus to the buffer, and then transfers the data from the buffer to the slave device. This allows for faster transfers of data out of the master device, and frees up the master""s bus faster for use in other data transfers.
The system controller or other subsystem can effect the transfer of data from the buffer to the slave device while also effecting further transfers of data over the master""s bus, thus achieving, from the point of view of the system controller, data transfers to the slave devicexe2x80x94or its associated bufferxe2x80x94at a rate limited only by the master""s bus width and the buffer size, and independent of the bus size of the slave device.
The invention thus provides for fast data transfers from a wide master""s bus even to devices having narrower buses, and accommodates a broad range of device bus widths. Devices thus need not have the same bus width as the master""s bus, providing economies and efficiency in their designs.